Memory systems, such as those based on Double Data Rate (DDR) Dynamic Random-Access Memory (DRAM), generally include a memory controller, a memory physical layer (PHY), and memory coupled to the memory controller via the memory PHY. Examples of the memory types can include, without limitation, Double Data Rate 4 (DDR4), Double Data Rate 5 (DDR5), Low Power Double Data Rate 4 (LPDDR4), and Low Power Double Data Rate 5 (LPDDR5). Additionally, the memory may come in a variety of module configurations, such as a single-inline memory module (SIMM), a dual in-line memory module (DIMM), or registered DIMM (RDIMM).
To facilitate communication between the memory controller and the memory, the memory PHY may implement a memory interface protocol defined by an industry specification, such as a version of the DDR PHY Interface (DFI) specification (e.g., DFI 5.0). In general, for DDR4 DRAM, memory configured as a single-memory channel device that interfaces with a single memory controller through a single memory PHY hardware interface. For DDR5 DRAM, the memory is generally configured as a two-memory channel device, where the two channels can operate independently of one another.
Memory controller connectivity can be a challenge with respect to certain multi-channel memory modules, such as a memory module that combines DDR4/DDR5, DDR5/LPDDR5, or LPDDR4/LPDDR5. For instance, a DDR4/DDR5 RDIMM may comprise a single channel of 72-bit DDR4 memory on the RDIMM and two channels of 40-bit DDR5 memory on the RDIMM. For such an RDIMM, in order for the one channel of 72-bit DDR4 memory to operate, and the two channels of 40-bit DDR5 memory to operate independently (as intended), two separate memory controllers (MCs) of the same type (e.g., two 72-bit MCs that each support 72-bit DDR4 memory and 40-bit DDR5 memory) may be used in the design (e.g., circuit design) of a memory system in order to minimize or obviate the need for changes to the design of the memory PHY of the memory system.
Unfortunately, using two separate MCs of the same type can have a large power, performance, area (PPA) impact on the memory system's design.